1. Technical Field of the Invention
The present invention relates to the reliability of ultra-thin dielectric films, such as mica, silicon dioxide, or Teflon, in semiconductor processing, and, in particular, relates to an ultra-thin dielectric process that tests the intrinsic properties of highly thin dielectric films at their operating field bias.
2. Description of Related Art
Ultra-thin dielectric films have been used extensively as insulating layers and protective barriers in microelectronic circuits. Conventional micro-electronic circuits are made of substrates, conductive bands, and highly thin dielectric materials. The reliability of ultra-thin dielectric affects the overall reliability of microelectronic circuits. Because an ultra-thin dielectric failure can result in catastrophic circuit failures, there exists a need to provide a reliable ultra-thin dielectric testing device and process that are capable of predicting the reliability of ultra-thin dielectrics in a cost-effective manner. In this regard, there also exists a need for a system and process that tracks the characteristics of dielectric breakdown and maintains meaningful quantitative data that can define statistical time-to-breakdown (t.sub.bd) distributions.
For ultra-thin dielectric films to be manufactured and applied in an efficient process, a practical and relatively simple process or device is essential. The performance and yield of semiconductor applications could be improved if the mechanics and control of ultra-thin dielectric testing processes could quantify ultra-thin dielectric lifetime within the electrical fields the ultra-thin dielectrics actually experience.
A number of theories of dielectric breakdown exists. Although the theories rely on different assumptions, two classes of breakdown are described by most theories. Ultra-thin dielectric breakdown may occur as a result of voids, stacking faults, precipitates, and scratches in the ultra-thin dielectric film or may occur as a result of intrinsic variations within the ultra-thin dielectric film. It is known that field breakdown induced by electrical stress is an intrinsic property of ultra-thin dielectrics. The study of intrinsic breakdown of ultra-thin dielectric films has made clear that a process or device that tests ultra-thin dielectric electrical properties is a reliable tool for estimating yields and predicting mortality rates of microelectronic circuits.
In conventional dielectric breakdown, the degradation of an ultra-thin dielectric film occurs in two stages. In the first stage, the ultra-thin dielectric is damaged by injecting electrons under a high field bias. Breakdown may be slow to occur as the decline of an ultra-thin dielectric is dependent on the magnitude of the applied field. During the second stage, the dielectric is subjected to a substantial tunneling conduction current that usually results in thermal breakdown due to the heating effects of the current flow. Although tunneling current flow may lead to thermal breakdown, it is known that ultra-thin dielectrics may withstand these currents and therefore a tunneling current condition may be a reversible phenomenon prior to the incidence of breakdown.
From a reliability approach, neither degradation stage is an accurate predictor of ultra-thin dielectric dependability. Although t.sub.bd distributions may be constructed by observing these processes, at best the life-cycle approximation is subject to error as conventional dielectrics are subjected to dynamic stress over their useful lives just as microelectronic devices experience a time-varying bias during ordinary use. Moreover, a dielectric decline due to detrimental exposure to an electric field is best approximated by subjecting the dielectric to an operating electric field for a period of time as a testing process should take into account the normal operating parameters the ultra-thin dielectric will be subjected to. This complex dynamic has not been recognized in the conventional art.
In one type of conventional ultra-thin dielectric testing process, the dielectric is subjected to a linearly ramping dc stress (voltage-ramp test). The voltage-ramp test begins at a use condition voltage or lower and linearly ramps until the ultra-thin dielectric is destroyed. Because the penetration of electrons through an ultra-thin dielectric film is approximately proportional to the ultra-thin dielectric film field, the voltage ramp-test may identify the failure point of an ultra-thin film that fails at relatively low applied fields, as the starting point of this process is at a use condition or lower voltage. However, the voltage-ramp test process fails to account for the dynamic stress dielectrics are subjected to as variations in electric fields may be random and do not normally occur in linear patterns. Moreover, the voltage-ramp test commonly fails to provide a segregation of dielectrics that fail at higher electric fields known to occur during the transient operation of microelectronic circuits.
In a second type of conventional ultra-thin dielectric testing process, the dielectric is subjected to a constant high electrical stress. The breakdown process consists of applying a static dc stress at a high voltage for the duration of the process. This process identifies dielectric breakdown when a sudden runaway current exceeds a predetermined threshold. Because ultra-thin dielectrics can sustain high conduction currents for a long time, this process generally fails to clearly indicate when breakdown occurs.
In a third type of conventional ultra-thin dielectric testing process, the dielectric is subjected to an exponentially ramping current stress (current-ramp test). In this process, a current is injected into a dielectric at a relatively low value and is then ramped exponentially until a breakdown occurs. In this process, the test begins at a higher electrical bias then the voltage-ramp test so that a measurable quantity of tunneling current is produced. Current injection occurs under a high voltage bias that usually induces a greater electrical field than the operating field the dielectric would normally be subjected to. Furthermore, it is known that the current-ramp test is generally limited in predicting ultra-thin dielectric reliability subjected to low electrical field bias.
In light of the strengths and weaknesses of the above processes, the conventional art teaches the selection and application of one test based on the predicted mortality rate of a sample. If it is assumed that defects generated under a low field bias will represent a small number of some larger population of defects, the conventional art suggests that the dielectric under test be subjected to a high field bias. However, the failure of ultra-thin dielectrics is a dynamic process in which a weakest-link characteristic will depend on the stress condition. Additionally, current measurements made at high biases do not clearly show when breakdown occurs. To this end, the role of an electrical field testing process should be carefully considered, as a lack of precision in emulating the use or operating condition can be harmful to the integrity of a microelectronic circuit.
The escalating requirements in microelectronic circuits, for example, sample/hold circuits and precision analog to digital converters besides many other circuits require an ultra-thin dielectric testing process that improves micro-electronic reliability, provides more accurate t.sub.bd statistical distributions, emulates the life-time operating conditions ultra-thin dielectrics are subjected to, simplifies the fabrication processes, applies to zero defect tolerance environments, and is cost-effective.